Memory Made Smarter: Weebit Nano’s Role in the AI Hardware Revolution

Artificial intelligence is transforming nearly every industry, from autonomous driving to healthcare to connected devices. But as AI models grow more complex, the biggest barrier to progress is no longer the raw compute; it’s the movement of data. Every time information travels between the memory and processor, precious speed and power are lost.

Memory plays a key role in overcoming this barrier. Our advanced Resistive RAM (ReRAM / RRAM) technology is not only a more efficient embedded non-volatile memory (NVM) than flash; it is also the foundation for new computing paradigms that can dramatically accelerate AI.

Smarter Memory for AI SoCs

Next-generation AI systems-on-chips (SoCs) are typically built on 22nm and smaller technologies. Unlike embedded flash, which cannot scale below 28nm, ReRAM continues to scale to advanced nodes. This allows the memory to be placed closer to the processor, a critical advantage for these systems.

By storing neural network weights directly on-chip, embedded ReRAM eliminates the need for external memories, reducing cost, power, size, and security risks. For today’s AI accelerators and microcontrollers, embedding ReRAM closer to processing units is a critical step forward. Near-memory computing (NMC) minimizes data movement by placing memory directly alongside logic. This enables faster access to weights and parameters, cutting latency and improving energy efficiency for AI inference, particularly in edge devices that must process data locally. In automotive and aerospace, ReRAM’s robust reliability, including AEC-Q100 qualification and radiation tolerance, ensures that AI systems can perform consistently even in the most demanding environments.

Above: We’ve already demonstrated the advantages of
ReRAM for near-memory computing

The next leap is towards computing inside the memory itself, called in-memory computing (IMC). ReRAM crossbars can perform matrix-vector multiplications (the core operation of neural networks) directly within the memory array.

By reducing the constant back-and-forth between memory and the processing unit, IMC promises significant speed-ups and lower power consumption for AI workloads. Weebit ReRAM is ideal for these architectures, with cost-efficiency, ultra-low power consumption, scaling advantages, analog behavior and ease of fabrication in the back end of the line (BEOL).

Looking even further ahead, Weebit ReRAM is naturally suited for neuromorphic computing, which mimics how the human brain processes information. According to Yole Intelligence, the neuromorphic computing market is expected to grow to $412 million by 2029 and $5.4 billion by 2034. The research firm expects that analog IMC solutions including those with ReRAM will ramp up starting in 2027.

The Weebit ReRAM cell functions similarly to a synapse in the brain, making it a promising solution. ReRAM devices can act as artificial synapses, with analog conductance levels representing synaptic weights. This opens the door to energy-efficient, brain-like chips capable of real-time learning and adaptation.

Above: The evolution of NVM as an enabler for AI

Collaborations Drive Innovation

Our partnership with CEA-Leti and collaborations with research institutes around the globe including ongoing neuromorphic studies, position Weebit technology as a building block for future brain-inspired processors.

Weebit is also now a member of the EDGE AI FOUNDATION, bringing our low-power, high-performance ReRAM to a dynamic community focused on uniting industry leaders and researchers to drive innovation, solve global challenges, and democratize edge AI technologies. We will be actively contributing towards this mission.

Above: A brief introduction to the EDGE AI FOUNDATION

In addition, we are collaborating with industry leaders on the development of ultra-low-power neuromorphic processing solutions under the NeMo Consortium, a three-year development program funded by the Israeli Innovation Authority. NeMo brings together research groups from major industry R&D teams and leading academia researchers across Israel. Its goal is to develop a technology infrastructure enabling neuromorphic processing capabilities for various edge products such as medical and security applications, with power consumption three orders of magnitude lower than the state of the art. The system will include dedicated hardware components, advanced AI software modules using spiking neural networks, and algorithms integrated with various sensors to enable ultra-low-power AI applications.

We are also working alongside a large group of companies under the NeAIxt project, which aims to solidify Europe’s position in edge AI and eNVM technology. The group is focused on enhancing AI enablers, evolving embedded NVM for edge applications, and demonstrating AI capabilities at both chip and system levels. The project will integrate advances in NVM technologies with cutting-edge MCU design to enable efficient in-memory computing. NeAIxt will address the entire edge AI value chain, from academia to industry, and from design to end-user applications, building on Europe’s strong technological foundation.

These are just a few of the areas where Weebit is pushing innovation in AI. You can read some of the latest papers in our Resources section.

The Road Ahead

From today’s embedded AI chips to tomorrow’s neuromorphic systems, Weebit is working to ensure that memory is no longer a bottleneck, but a driver of innovation. By making memory smarter, we are helping shape a new era of computing where intelligence is faster, more efficient, and available everywhere.

The post Pushing the Boundaries of Memory:<br>What’s New with Weebit and AI appeared first on Weebit.

When people think of semiconductor companies, they often picture vast factories filled with billion-dollar equipment. But Weebit Nano operates in a very different way.

If you’ve read our blog before, then you know that we develop Resistive RAM (ReRAM / RRAM), an advanced non-volatile memory (NVM) technology designed for a new era of AI-powered edge devices, automotive electronics, and other demanding applications. But rather than manufacturing the chips ourselves, we license our technology to companies that integrate it into their own semiconductor products.

This approach is known as semiconductor intellectual property (IP) licensing model, a model that is well established among global semiconductor leaders such as Arm and Ceva. If you don’t know about this model, it’s worth understanding why this model is so compelling.

Asset-light, high-margin, and scalable

Traditional chip manufacturing requires enormous capital investment in fabrication plants (“fabs”) and equipment. Advanced fabs today cost tens of billions of dollars to set up. In contrast, an IP licensing company like Weebit focuses on developing and perfecting its technology. It then licenses it to customers who either have their own manufacturing capabilities or use foundries to outsource manufacturing of their designs.

Weebit provides two types of licenses: manufacturing and design. A manufacturing license gives a fab the right to manufacture devices which include our technology, and a design license allows a product company to embed our technology into their chip.

In the case of a manufacturing license, the customer will also pay a Non-Recurring Engineering (NRE) fee to cover the cost of the technology transfer and qualification. In the case of a design license, the customer might ask for some modifications to the memory module, in which case they will pay NRE fees on top of the design license fees. Once their chips go into mass production, Weebit will receive a royalty payment for every chip sold that uses our technology.

Above: The IP business model can look slightly different, depending on the type of
company we are licensing to (e.g., a foundry, IDM, or product company).

Because we don’t need to build factories or maintain inventory, our operating costs are relatively low, and our gross margins can be very high. Looking at comparable IP businesses, such margins can often exceed 90%. This means that once royalty streams begin, revenues can scale quickly without a corresponding rise in expenses.

Long-term, sticky revenues

Another strength of the IP licensing model is its staying power. Once our technology is embedded in a customer’s chip design and manufacturing process, it tends to remain there for the lifetime of that product. For Weebit, that can mean many years of recurring royalty payments from a single design win.

The result is a growing base of long-term, high-margin revenue streams that can compound over time as we add more customers and applications.

Global market opportunity

The global semiconductor market is vast, and with flash memory reaching its scaling limits, there is a growing need for next-generation embedded memory technologies like ReRAM. While some companies develop and use their own ReRAM internally, the majority of the market is open to external licensing. That’s the opportunity Weebit is targeting.

We’ve already signed initial license agreements with major players including DB HiTek (a foundry) and onsemi (an IDM), and we’ve recently signed our license to an end product company in the U.S. We are working towards additional agreements with other such companies across key sectors.

You can read my earlier article, World IP Day: A Time to Reflect on the Value of Semiconductor IP, to learn more about the different types of semiconductor IP and how such solutions are delivered. You can also read more about Weebit’s technology, market position, and licensing strategy in this recent article where Andrew Johnston, Industrial Analyst from MST Access, explores why the IP model is such a powerful driver for our ReRAM ambitions: How Weebit Nano’s IP strategy is fuelling ReRAM ambitions.

The post Why Weebit’s IP Licensing Model Matters appeared first on Weebit.

As more companies seek to integrate our IP into their fabs and products, the momentum behind Weebit ReRAM is building. That’s why we are focused on scaling every part of our business to meet this growing demand.

Building to Support Growth

Scaling effectively means much more than just adding headcount—it requires deliberate planning, the right infrastructure, and a culture of operational excellence. Our goal is to support multiple fab projects and product engagements in parallel, without compromising on speed, quality, or customer experience, and doing so with the minimal number of people.

To that end, we’ve launched a company-wide initiative to enhance our infrastructure, tools, and methodologies. We are automating key workflows, building centralized systems to manage and analyze large volumes of wafer data, and implementing processes to improve traceability and reporting. These efforts are all designed to ensure that every customer project runs smoothly and efficiently, living up to our commitment that each and every customer is successful in incorporating Weebit ReRAM into their fab/product.

Importantly, we’re doing this with cost-effectiveness in mind. Unlike many companies at this stage of growth, Weebit benefits from being an IP provider. We don’t manage physical inventory or complex supply chains—which allows us to stay lean and agile while we scale.

Customer Success: At the Core of Everything We Do

At the heart of our scaling strategy is an unwavering commitment to customer success. Weebit is committed to ensuring every customer project using its ReRAM will be successful, and that no project will fail because it used Weebit ReRAM.

We’ve established a formal Project Management Office (PMO) to define clear—and as automated as possible—operating procedures. We appointed Lilach Zinger to lead our newly established Customer Success team. With over 20 years of experience at Tower Semiconductor—including as VP of Operations of Fab1—Lilach brings deep knowledge fab challenges, and what they need to succeed. Under her leadership, we’re building the systems and structures to manage multiple fab engagements simultaneously while delivering a consistently high level of service.

Designed to Scale: Talent and Technical Depth

Scaling requires not only process and technology but also people. We are growing our team carefully and strategically, bringing in top-tier talent across process, device, analog, and digital design. With hubs in Israel and France, we have access to a rich talent pool—and our long-standing university collaboration pipeline helps us bring in promising new engineers who are trained in ReRAM from day one.

Our culture is rooted in technical excellence and teamwork. We’re building a company where every employee contributes to customer success, continuous innovation, and operational strength.

Governance and Leadership Ready for the Next Level

As we grow, we are evolving our corporate structure to reflect our status as a leading public company. We’ve reorganized our board, welcoming Naomi Simson and Anne Templeman-Jones and establishing board committees that meet the standards of an ASX200/100-level company. We also transitioned Yoav Nissan-Cohen to be a non-executive director to further enhance board independence.

We’ve implemented comprehensive corporate governance procedures, including a clear Business Continuity Plan (BCP). This plan was successfully put to the test in the ongoing situation in the Middle East, helping ensure there will not be any delays in any milestone, not even by one day.

Looking Ahead

Weebit has entered a pivotal stage as we scale our operations to support a growing roster of customers. We are committed to signing several agreements with additional fabs, as well as with product companies, before the end of 2025. We are well-funded, strategically focused, and organizationally aligned to meet the challenge. With ReRAM moving into the mainstream, we are positioned to be the partner of choice for companies looking to integrate advanced NVM into their SoC designs.

Every step we’re taking, across infrastructure, customer success, engineering, and governance, is designed to ensure that every customer who chooses Weebit ReRAM achieves success. We’re building not just for today’s growth, but for the long-term future of our company and the industry we’re helping to shape.

The post Scaling for Success:<br>How Weebit is Preparing for its Next Phase of Growth appeared first on Weebit.

AI training happens in the cloud because it’s compute-intensive and highly parallel. It requires massive datasets, specialized hardware, and weeks of runtime. Inference, by contrast, is the deployment phase — smaller, faster, and often done at the edge, in real time. The cloud handles the heavy lifting; the edge delivers the result. Now, recent advances in resistive memory technology are making edge AI inferencing more energy-efficient, secure, and responsive.

At the 2025 IEEE Symposium on VLSI Technology and Circuits, researchers from CEA-Leti, Weebit Nano, and the Université Paris-Saclay presented a breakthrough in “on-chip customized learning” — demonstrating how a ReRAM-based platform can support few-shot learning using just five training updates.

Few-shot learning (FSL) is an approach where AI models learn new tasks with only a handful of examples. It is very useful for edge applications, where devices must adapt to specific users or environments and can’t rely on large, labeled datasets.

The team didn’t just train a model — they showed that a memory-embedded chip could adapt in real-time, at the edge, without requiring cloud access, long training cycles, or power-hungry hardware. The core enabler is a combination of Model-Agnostic Meta-Learning (MAML) and multi-level Resistive RAM (ReRAM or RRAM).

MAML provides a clever workaround that can enable learning in power-constrained edge devices. Instead of training from scratch, it trains a model to learn. During an off-chip phase, the system builds a general-purpose model by exposing it to many tasks. This “learned initialization” is then deployed to edge devices, where it can quickly adapt to new tasks with minimal effort.

This means:

• No need for the cloud – minimizing bandwidth and latency
• Minimal data required – minimizing compute requirements at the edge
• Massive time and energy savings

Executing this on edge hardware requires memory technology that can keep up — and that’s where ReRAM comes in.

Because ReRAM is a non-volatile memory that supports analog programming, it is ideal for low-power and in-memory compute architectures. ReRAM can store information as varying conductance states, which can then represent the weights (numerical values that represent the strength or importance of connections between neurons or nodes in a model) in neural networks.

However, ReRAM also comes with challenges — notably variability and some limits on write endurance. Few-shot learning helps overcome both.

Reducing Write Cycles with MAML

In terms of endurance, the key is in leveraging MAML, which enabled the research team to reduce the number of required write operations by orders of magnitude. Instead of millions of updates, they showed that just five updates — each consisting of a handful of conductance tweaks — were enough to adapt to a new task.

For the experiments, a chip fabricated on 130nm CMOS was used which has multi-level Weebit ReRAM integrated in the back end of line (BEOL). The network architecture had four fixed convolutional layers and two trainable fully-connected (FC) layers. Weights in the FC layers were encoded using pairs of ReRAM cells, storing the difference in conductance between them.

Training was carried out using a “computer-in-the-loop” setup, where the system calculated gradients and issued write commands directly to the ReRAM crossbars. In a full deployment, this would be managed by a co-integrated ASIC.

The learning task? Character recognition from the Omniglot dataset, a popular benchmark in FSL. The chip was pre-loaded with the MAML-trained parameters and fine-tuned on-device to recognize new characters using only five gradient updates.

The result:

• Starting at 20% accuracy (random guess)
• Reaching over 97% accuracy after five updates
• Energy use of less than 10 μJ for a 2kbit array

For an optical character recognition (OCR) application using AI with a 2Kbit array, energy consumption of less than 10 μJ represents excellent energy efficiency compared to typical industry benchmarks. This level of power consumption places such a system in the ultra-low-power category suitable for edge AI applications and battery-powered devices.

Programming Strategies to Mitigate Against Drift

In ReRAM conductance levels can drift over time, and adjacent states may overlap, introducing noise. To tackle this, the team tested multiple programming strategies:

• Single-shot Set: Simple, fast, but inaccurate
• Iterative Set: More precise, but slower
• Iterative Reset: Useful for low conductance states
• Hybrid strategy: A blend of both, offering the best balance

The hybrid strategy proved most effective, reducing variability and improving long-term retention. After a 12-hour bake at 150°C (equivalent to 10 years at 75°C) the system still maintained over 90% of its accuracy.

This is critical for commercial deployment, where temperature fluctuations and data longevity are real-world concerns.

Looking Ahead

This research points to a compelling future for AI at the edge:

• Learn locally: Devices can customize their behavior to individual users
• Stay secure: No data needs to be sent to the cloud
• Save time and energy: Minimal training and in-memory compute keep power low
• Scale affordably: Meta-training can be centralized and shared across devices

And because the platform uses ReRAM, the entire system benefits from ultra-low standby power and reduced silicon area.

This work is more than a proof of concept, it’s a signpost. As more AI applications move to the edge, we’ll need memory technologies that support not just inference, but real learning. ReRAM is emerging as one of the few candidates that can deliver on that vision, especially when paired with smart algorithms like MAML.

View the presentation, “On Chip Customized Learning on Resistive Memory Technology for Secure Edge AI” from the 2025 IEEE Symposium on VLSI Technology and Circuits here.

The post Enabling ‘Few-Shot Learning’<br>AI with ReRAM appeared first on Weebit.

Resistive RAM (ReRAM or RRAM) is the strongest candidate for next-generation non-volatile memory (NVM), combining fast switching speeds with low power consumption. New techniques for managing a memory phenomenon called ‘relaxation’ are making ReRAM more predictable — and easier to specify for real-world applications.

What is the relaxation problem in memory? Short-term conductance drift – known as ‘relaxation’ – presents a challenge for memory stability, especially in neuromorphic computing and multi-bit storage.

At the 2025 International Memory Workshop (IMW), a team from CEA-Leti, CEA-List and Weebit presented a poster session, “Relaxation-Aware Programming in RRAM: Evaluating and Optimizing Write Termination.” The team reported that Write Termination (WT), a widely used energy-saving technique, can make these relaxation effects worse.

So what can be done? Our team proposed a solution: a modest programming voltage overdrive that curbs drift without sacrificing the efficiency advantages of the WT technique.

Energy Savings Versus Stability

Write Termination improves programming efficiency by halting the SET (write) operation once the target current is reached, instead of using a fixed-duration pulse. This reduces both energy use and access times, supporting better endurance across ReRAM arrays.

It’s desirable, but problematic in action.

Tests on a 128kb ReRAM macro showed that unmodified WT increases conductance drift by about 50% compared to constant-duration programming.

In these tests, temperature amplified the effect: at 125°C, the memory window narrowed by 76% under WT, compared to a fixed SET pulse. Even at room temperature, degradation reached 31%.

Such drift risks destabilizing systems that depend on tight resistance margins, including neuromorphic processors and multi-level cell (MLC) storage schemes, where minor shifts can translate into computation errors or data loss.

The experiments used a testchip fabricated on 130nm CMOS, integrating the ReRAM array with a RISC-V subsystem for fine-grained programming control and data capture.

Conductance relaxation was tracked from microseconds to over 10,000 seconds post-programming. A high-speed embedded SRAM buffered short-term readouts, allowing detailed monitoring from 1µs to 1 second, while longer-term behavior was captured with staggered reads.

This statistically robust setup enabled precise analysis of both early and late-stage relaxation dynamics.

To measure stability, the researchers used a metric called the three-sigma memory window (MW₃σ). It looks at how tightly the memory cells hold their high and low resistance states, while ignoring extreme outliers.

When this window gets narrower, the difference between a “0” and a “1” becomes harder to detect — making it easier for errors to creep in during reads.

By focusing on MW₃σ, the team wasn’t just looking at averages — they were measuring how reliably the memory performs under real-world conditions, where even small variations can cause problems.

Addressing Relaxation with Voltage Overdrive

Voltage overdrive is the practice of applying a slightly higher voltage than the minimum required to trigger a specific operation in a memory cell — in this case, the SET operation in ReRAM.

Write Termination cuts the SET pulse short as soon as the target current is reached. That saves energy, but it also means some memory cells are just barely SET. They’re fragile — sitting near the edge of their intended resistance range. That’s where relaxation drift kicks in: over time, conductance slips back toward its original state.

So, the team asked a logical question:

“What if we give the cell just a bit more voltage — enough to push it more firmly into its new state, but not so much that we burn energy or damage endurance?”

Instead of discarding WT, the team increased the SET voltage by 0.2 Arbitrary Units (AU) above the minimum requirement.

Key results:

• Relaxation dropped to levels comparable to constant-duration programming
• Memory windows remained stable at both room and elevated temperatures
• WT’s energy efficiency was mostly preserved, with only a ~20% increase in energy compared to unmodified WT

Modeling predicted that without overdrive, 50% of the array would show significant drift within a day. With overdrive, the same drift level would take more than 10 years, a timescale sufficient for most embedded and computing applications.

Balancing Energy and Stability

The modest voltage increases restored conductance stability without negating WT’s energy and speed benefits. Although the overdrive added some energy overhead, overall consumption remained lower than that of fixed-duration programming.

This adjustment offers a practical balance between robustness and efficiency, critical for commercial deployment.

As ReRAM moves toward wider adoption and is a prime candidate for use in neuromorphic and multi-bit storage applications, conductance drift will become a defining challenge.

The results presented at IMW 2025 show that simple device-level optimizations like voltage overdrive can deliver major gains without requiring disruptive architectural changes.

Check out more details of the research here.

The post Relaxation-Aware Programming in ReRAM:<br>Evaluating and Optimizing Write Termination appeared first on Weebit.

In AI inference, trained models apply their knowledge to make predictions and decisions. To achieve lower latency and better security, the world is transitioning steadily towards performing AI inference at the edge – without sending data back and forth to the cloud – for a wide range of applications.

Because edge devices are often small, battery-powered, and resource-constrained, it’s important that the computing resources enabling this process and the associated memories are ultra-low-power and low-cost. This is a challenge for AI workloads, which are known to be power-hungry.

The industry has been making progress towards lower power computation largely by moving to more advanced process nodes. This enables more performance with greater energy efficiency in smaller silicon area. However, non-volatile memories (NVMs) haven’t been able to scale to advanced nodes along with logic. Today we see advanced chips in process nodes of 3nm. At the same time, embedded flash memory is unable to scale below 28nm. This means that NVM and AI engines are often manufactured at very different process nodes and can’t be integrated on the same silicon die.

This is one of many reasons why the industry is exploring new memory technologies like Weebit ReRAM (RRAM).

The need for a single-die solution

Neural Network coefficients (often referred to as NN weights), which are used for computations by the inference engine, need to be stored in an NVM, so that when the system is powered-on these coefficients are available for compute workloads. Because it’s not possible to integrate flash and an AI engine on one die below 28nm, it is standard practice to implement a two-die solution, with one die at a small process node used for computing, and the other die at a larger process node used for storing the coefficients. These two dies are then either integrated in a single package or in two separate packages. Either way, such a two-die solution is more expensive and has a bigger footprint. Also, copying the coefficients from an external flash to an on-chip SRAM in the AI chip is very power hungry and creates latencies. In addition, the fact that the coefficients are moved from one chip to the other creates a security risk, as it is easy to eavesdrop this communication.

The ideal solution for edge AI computing from power, latency, cost and security perspectives is a single die that hosts both memory and compute.

A scalable, single-chip solution with ReRAM

Embedded ReRAM is the logical alternative to flash for edge AI. ReRAM is significantly more energy efficient than flash, and it provides better endurance and faster program time. Since it is scalable to advanced processes, ReRAM enables a true one-chip solution, with NVM and computing integrated on the same die.

ReRAM-enabled SoCs are less expensive to manufacture because they only require two additional masks in the manufacturing flow, while flash requires 10 or even more such masks. Embedding ReRAM into an AI SoC would eliminate the need for off-chip flash devices and replace most of the large on-chip SRAM used to temporarily store the NN weights. Since the technology is non-volatile, the system can boot much faster as there is no need to wait for loading the AI model and firmware from external NVM, and the security risk is removed. ReRAM is also much denser than SRAM, so more memory can be integrated on-chip to support larger neural networks for the same die size and cost, while enabling more advanced AI algorithms.

New Demo: ReRAM for ultra-low-power edge AI

A new demonstration showcases the advantages of Weebit ReRAM-powered edge AI computing. Developed through a collaboration between Weebit and Embedded AI Systems Pte. Ltd. (EMASS), a subsidiary of Nanoveu, the gesture recognition demo shows Weebit ReRAM working with EMASS’s energy-efficient AI SoC, the EMASS ECS-DOT. The demo emphasizes the ultra-low-power consumption of ReRAM and its ability to enable instant wake-up AI operations. In the real world, such a system could be used to detect driver activity for advanced driver safety systems, or it could be used for safety/surveillance, robotics, and many other applications.

ECS-DOT is an edge AI chip manufactured in a 22nm process that delivers significant energy efficiency and cost advantages, with best-in-class AI capacity. In the demo, ECS-DOT loads the neural network weights from Weebit ReRAM where they are being stored. As noted earlier, this is a powerful feature of ReRAM – it can be used to replace the large on-chip SRAM to store the NN weights, as well as the CPU firmware.

Weebit ReRAM isn’t yet integrated into the ECS-DOT SoC, so the proof-of-concept demo shows a two-chip solution with the 22nm Weebit demo chip communicating with the EMASS chip over an SPI bus. In an end solution, the ReRAM would be integrated on-chip, eliminating latency, cost and security risks, and demonstrating even lower power consumption. Such integration can enhance system performance and also ensure scalability and sustainability, paving the way for smarter, more autonomous edge devices.

Above: ultra-low-power ReRAM based gesture recognition system
with Weebit ReRAM and EMASS AI SoC

EMASS recently made a strategic pivot away from MRAM technology and is embracing ReRAM. The company says that ReRAM is better able to support next-generation systems in IoT, automotive, and consumer electronics.

Looking Ahead

Research is now underway to bring memory and compute resources even closer together through analog in-memory compute. In this paradigm, compute resources and memory reside in the same location, so there is no need to ever move the coefficients. Such a solution using ReRAM will be orders of magnitude more power-efficient than today’s neural network simulations on traditional processors.

You can see our new demo video here:

The post ReRAM-Powered Edge AI:<br>A Game-Changer for Energy Efficiency, Cost, and Security appeared first on Weebit.

When it comes to cars, safety and reliability are paramount. That’s why almost every single part of a car must meet standards and regulations designed for the specific stresses the component could face throughout its lifetime. This includes everything from engine components to the infotainment cluster to the window glass. Pretty much the only standard parts of a car that aren’t subject to such controls are the cup holders.

The strictest standards are those for safety-critical components like brakes, seatbelts and airbags, tires, steering systems, and engine control and monitoring. These systems must comply with multiple regulatory and industry standards – including passing crash and durability tests as well as compliance checks – because they directly impact passenger safety.

When it comes to vehicle electronics, there are similar strict reliability tests, especially with the increasing complexity and proliferation of technologies like advanced driver assistance systems (ADAS). For integrated circuits (ICs) including microcontrollers (MCUs), sensors and memory chips, the qualification standard is called AEC-Q100.

AEC-Q100 is a stress test qualification established by the Automotive Electronics Council (AEC), an organization originally formed by Chrysler, Ford, and GM to establish common part qualification and system quality standards. The council provides an official document that outlines the AEC-Q100 qualification process called Stress Test for Qualification for Integrated Circuits.

If a device is qualified to AEC-Q100, it means that it has passed the specified stress tests and guarantees a certain level of quality/reliability. This makes AEC-Q100 qualification important not only for automotive applications; knowing a technology is AEC-Q100 qualified tells designers of all applications that it is very high quality, so they can feel more confident when using it.

Withstanding Harsh Conditions

AEC-Q100 defines four ambient temperature ranges (known as ‘grades’) designed to cover the several different thermal environments in which automotive applications operate. This classification enables designers to select the components that align best with their needs. The lower the grade; the more qualification constraints are required. AEC-Q100 defines four ambient operating temperature ranges:

• Grade 0: -40°C to +150°C
• Grade 1: -40°C to +125°C
• Grade 2: -40°C to +105°C
• Grade 3: -40°C to +85°C

Grade 0 components are rated for extreme conditions and can handle the harshest environments in a vehicle. This includes devices used in powertrain and engine control, and many others that must be able to withstand high temperatures, vibration, and continuous operation.

Beyond the ability to reliably withstand harsh conditions, automotive ICs must also be designed for safety, security and longevity. Some requirements can be quite different than those in consumer markets.

Above: consumer versus automotive requirements

Non-Volatile Memory in Automotive

Non-volatile memory (NVM) for automotive must support fast boot, instant response, and frequent over-the-air (OTA) updates. Increasingly, auto makers are looking to integrate an MCU and embedded NVM in a BCD process to replace solutions that previously used an external standalone memory. And, as many SoCs move to advanced nodes to meet performance requirements, companies are looking to alternatives to embedded flash like Weebit ReRAM.

ReRAM (RRAM) is reliable at high temperatures, it can withstand harsh conditions like vibration and electromagnetic interference (EMI), and it has high endurance, fast switching speed, long-life, and innate security. It can also effectively scale to the most advanced process nodes.

When supplying NVM for automotive applications, it must achieve AEC-Q100 qualification.

Accelerated Stress Testing

To achieve AEC-Q100 qualification, it’s necessary to test three unique lots which ran at different times in the production line, with 77 samples per lot to assure the statistical significance level for very low failure rates. The samples must undergo 1,000-2000 hours of accelerated testing with zero failures – for each of the specified tests. For a discussion of accelerated testing, see our previous article, “Compressing a Lifetime’s Worth of Stress: ReRAM Qualification Explained.”

Tests include those for endurance, data retention, and operating life. To rate for Grade 0 applications, the samples must repeatedly demonstrate 150°C operation for up to 100K endurance cycles, with very low bit error rate (BER) throughout. The specific flow and tests are outlined in the AEC-Q100 Rev D1 Non-Volatile Memory Program/Erase Endurance, Data Retention and Operating Life Test.

Looking beyond the baseline stress tests, there are also specific mission profiles that we must consider.  The qualification flow mentioned above gives a great deal of confidence to potential customers, however, when selecting a part for their specific applications, companies must look at the specific use case surrounding a part.

A part may be expected to reach the highest temp of 175⁰C for only 0.02% of the time and -40⁰C only 4.20% of the time, but for most of the time, the part operates at much more moderate temperatures. See an example of such a mission profile in the table below.

Commonly, companies put together sets of numbers that estimate the percentage of time a part will be at a certain temperature, then calculate the numbers to determine whether the expected real-life stress is expected to be less than or more than the stress that was applied during qualification. If the result is less than the qualified time, customers can be confident the part will not fail from aging issues during its normal lifetime.

Above: An example of a calculation for an automotive mission profile

Conclusion

Having an embedded NVM module that is fully qualified for AEC-Q100 is the first big step to getting the NVM designed into automotive applications – as well as other applications in harsh environmental conditions. Automotive end products that use devices in a new process must be qualified for AEC-Q100. Each time a module incorporating a specific technology like Weebit ReRAM is qualified, it demonstrates that the technology is mature, it is thermally stable with high endurance, and it reaches the standard of zero defects per million parts.

In assuring quality in each part of the vehicle, every single player in the supply chain must ensure their part adheres to quality standards. From IP makers like Weebit to semiconductor companies, product companies, foundries, systems companies and automakers – and others in between – functional safety is a clear priority. At Weebit we are dedicated to ensuring our IP is proven ready for integration in automotive applications today.

AEC-Q100 qualification is a sign of high quality, not only for automotive, but for all application domains.

Want to learn more about the potential of Weebit ReRAM in automotive?
Check out this recent article in EE Times, which touches on the topic: Onsemi’s Treo Taps Weebit ReRAM.

The post The Road to AEC-Q100 Qualification appeared first on Weebit.

It’s January 7, 2025, and today, Weebit Nano is 10 years old. What an amazing milestone!

When the company began in 2015, we had ideas based on the work of Prof. James Tour from Rice University. The ideas were around resistance as the basis of memory, and while still in the research phase, Weebit’s founders knew the concepts were solid, and also knew that very soon the industry would need a replacement for flash memory.

That year the company hired its first engineer, Amir Regev, who today is Weebit’s VP Quality & Reliability. One of Amir’s first projects was to look for an excellent R&D partner, and after much due diligence, the company engaged with CEA-Leti, the French research organization who continues as our strategic R&D partner today. It was the beginning of an amazing partnership.

In 2016, Weebit hired its first PhD in France, Giuseppe Piccolboni, and in 2017, the company established its French subsidiary.

Weebit was fortunate in the early days to catch the attention of Dadi Perlmutter, who had retired from his most recent position at Intel as EVP, Chief Product Officer and GM of the Intel Architecture Group, overseeing all the company’s products. He agreed to become the Chairman of the Weebit Board of Directors.

Getting funding was a big challenge in the days when VCs were focused on cyber, automotive and the initial phases of AI. We were lucky that at the same time, the Australian Stock Exchange (ASX) was looking to expand its roster of listed companies beyond the many focused on mining, energy and finance to include more technology companies. As part of this effort, the ASX sent several delegations to Israel to investigate the possibilities, and numerous Israeli technology companies including Weebit decided to list on the ASX.

Weebit’s former CEO, Yossi Keret, worked with Dadi and Ashley Krongold, one of our very first investors, to list on the ASX through a reverse takeover in August 2016. Yossi focused on setting up the company’s initial infrastructure in Israel, France and Australia, including hiring our CFO, Alla Felder. Shortly thereafter, Yossi had to step down for personal reasons and recommended me to replace him. (Thank you for that, Yossi!)

I joined the company in October 2017, with only two engineers on board and a technology that was still in university-level R&D. Dadi brought on board Atiq Raza, a legend in the semiconductor space (previously President and COO of AMD; Chairman and CEO of RMI – just a bit of his deep experience), as well as Yoav Nissan-Cohen, who did a PhD in Device Physics under Prof. Dov Frohman, the inventor of the first digital non-volatile memory (NVM). Yoav was also a founder of Tower Semiconductor, one of the top 10 foundries. Yoav became an executive director on the Weebit Board, helping guide technology development in the early days.

2018 was a year of transition for Weebit. On the technical side we delivered a 1Mb array and we started hiring a strong team. In 2019 we overcame a tough financial situation and started pushing for partnerships and looking for initial customers. At the time we had more of a focus on the very large semiconductor market in China, but when COVID hit, together with a growing trade war, we decided to shift our focus to the rest of the world.

Despite all odds, 2020 became a major year of growth. We had a good capital raise in June, followed by another in November. In October of that year, we completed the ReRAM (RRAM) technology stabilization process. At the same time, we hired three well-known experts to set up our executive staff: Ishai Naveh as CTO, leading our device and process work; Ilan Sever as VP R&D, leading analog and digital design efforts; and Eran Briman as VP Marketing and Business Development. In 2022 we brought on board Gabriel Molas, with close to 20 years of ReRAM research experience at Leti, to be our Chief Scientist.

Technical progress continued with the qualification of our technology at Leti (on STMicro wafers) at 85⁰C and then 125⁰C. We closed our first licensing agreement with SkyWater, and showed we know how to transfer the recipe and achieve qualification there too. This led to a licensing agreement with DB HiTek, where we are now focused on moving towards full qualification.

In 2023 and 2024 we completed the executive team, adding Gideon Intrater as an Advisor to the CEO, and Issachar Ohana as Chief Revenue Officer.

And now, just before our 10^th anniversary, we closed a licensing agreement with one of the leading integrated device manufacturers (IDMs), onsemi, starting 2025 with a bang!

10 years ago, the world knew it wanted a new NVM, but it was not clear what that would look like. There were MRAM, FeRAM, PCM, Optane, 3D-Xpoint, ReRAM and others. There were other companies developing ReRAM, already trying to commercialize years before Weebit.

However, as time passed, it became clear that many of these technologies were too expensive to manufacture or had other side effects (like sensitivity to magnetic fields), and today it is clear that the leading technology emerging from the pack is ReRAM. Other ReRAM developers tried using non-standard materials and tools to implement ReRAM, and many failed, leaving Weebit Nano as one of the only three qualified ReRAM technologies to-date, and the only independent supplier of qualified ReRAM in the market.

Over the past 10 years as we have pushed Weebit ReRAM from research towards production, we have had many ups and downs, but one of the key traits shared by our team members is their persistence. Because of this, we persist in our goal to deliver excellent, cost-effective technology towards becoming the #1 embedded NVM vendor. Interestingly, this persistence is reflected in our technology itself – ReRAM as a non-volatile memory is a persistent memory that retains its data even when power is turned off.

I am thankful for the opportunity to lead Weebit, and for the amazing Board and team we have. And I am very thankful to our loyal shareholders, many of whom have been with us almost from the start.

What a journey it has been! And it is only the beginning, as we look towards the next 10 years, which will be years of commercialization and expansion, with the vision of becoming the #1 supplier of embedded NVM and also developing a discrete solution.

We know that Weebit has the recipe for success. Our robust and fully qualified technology is continuously improving under the hands of a strong R&D team, including 13 PhDs and experts in all four pillars of ReRAM: Device, Process, Analog design and Digital design, all under the leadership of a very experienced and focused management team. With our solid team, robust technology, several commercial deals completed, and having recently raised A$50 million, we are well positioned to make our vision a reality.

2025 is shaping up to be a very exciting year, and a great start for the next 10 years!

The post Weebit Nano Turns 10:<br>Only the Persistent Survive appeared first on Weebit.

Awhile back, I wrote an article describing the concept of technology transfer, explaining that when a fab gets ready to start manufacturing a new technology, it must work closely with the technology developer to create the perfect recipe – including the materials, process, tools and equipment, and other variables.

In this article, I would like to focus specifically on the materials piece of that recipe. I’ll explain what ‘materials’ are in the context of semiconductor manufacturing and explore what we mean at Weebit Nano when we talk about our use of ‘fab-friendly materials’ as an advantage of Weebit ReRAM.

Let’s define ‘materials’

‘Materials’, according to the Merrian Webster dictionary, are “the elements, constituents, or substances of which something is composed or can be made.”

Manufacturing most goods today includes myriad materials that are used in a complicated chains of processing steps. Take leather goods for instance. There is a broad set of materials needed to process the finished leather, before it becomes ready to be made into end products like shoes and bags. Materials include those that comprise the end products, such as the hides themselves, as well as dyes, waxes and oils. There is an even broader mix of materials that are used in the fabrication process and then thrown away, such as cleaning agents, preservation and tanning materials and finishing agents.

Similarly, when we talk about semiconductors, we are talking not only about the materials that comprise the actual semiconductors themselves (in the stack and interfaces), but also about the substances that are used in the fabrication/manufacturing of the wafers and then disposed of.

Some materials are uniformly applied, while others are applied in patterns. In leather goods, this is done through techniques such as embossing and engraving using predefined texture plates. In semiconductors, many materials are applied using photomasks through which the materials are deposited on specific areas of the wafer.

Materials used in semiconductor manufacturing

Some materials like copper and aluminum are very good conductors of electricity, and others like rubber and wood have insulating properties and therefore prevent conductivity. Semiconductor materials have properties of both conductors and insulators, enabling conductivity under certain controllable conditions like temperature, pressure, and other process parameters. These materials are critical to electronic devices, enabling control of the electricity flow.

According to the IEEE, the most widely used semiconductor materials are silicon (Si), germanium (Ge), and gallium arsenide (GaAs). Germanium was used early on and is still used for some applications, but silicon, which is the second most abundant element in the earth’s crust, has been used extensively in semiconductors since the 1950s.

Silicon is efficient and economical to extract, purify and crystallize, and it’s straightforward to mass-produce. Within standard CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing flows, silicon or compounds of silicon are the most widely used. Since pure silicon is more of an insulator than a conductor, a process called ‘doping’ is used to add tiny impurities (atoms of other materials) to the silicon to make it more conductive.

There are also materials used in manufacturing that are built into the stack for metal layers, interconnects, conductive barriers, and so on. Then there are the materials that are disposed of after use. Like the cleaning, curing and tanning agents we need to process leather, these materials – including gases, solvents, polymers, and others – are not actually part of the end products, but they are needed for processing.

Above: an example CMOS process courtesy of https://www.scl.gov.in/cmos.html

“Friendly” versus “unfriendly” materials

Choices of materials are often based on their inherent electrical properties, changes under different environmental conditions, interactions with other materials, and their compatibility with existing CMOS technologies.

This latter consideration is something we refer to at Weebit as being ‘fab friendly’ and it’s a differentiator for our ReRAM (RRAM).

An article written awhile back by my colleague, Eran Briman details an environmental initiative we completed with our R&D partner CEA-Leti which clearly shows the difference between friendly and unfriendly materials. The initiative compared Weebit ReRAM to MRAM technology, and results showed that the environmental impact of ReRAM is much lower than that of MRAM. Read Eran’s article to learn more about the criticality of various materials used in semiconductor manufacturing, and why the materials used in Weebit ReRAM are much friendlier than those used in MRAM.

Unfriendly materials

Critical and rare earth materials are very expensive often due to the cost of their extraction. Their extraction is also often very unfriendly to the environment, and their use can be complicated by political factors. Rare earth materials can add huge costs and complexities to the manufacturing process, so minimizing their use is very important.

Some materials aren’t rare earth materials, but they still aren’t very friendly – whether to the environment, or to adoption by a fab. Using more exotic materials can require additional dedicated clean room space, vacuum technology, extra tooling, standalone etch and deposition tools, special cleaning protocols, different wafer handling processes, and myriad other considerations. There can also be added issues with equipment degradation, sewage and recycling requirements.

Materials like iron (Fe) and Nickel (Ni) are considered unfriendly to CMOS fabrication, so strict protocols are followed to prevent contamination from these metals. Even trace amounts can lead to significant reductions in performance, stability, and reliability, so their use requires specialized equipment and cleanroom conditions to maintain the purity and performance of the devices.

Another example is PZT (a combination of lead zirconate (PbZrO₃) and lead titanate (PbTiO₃), which is used in medical imaging equipment, sensors and actuators, energy harvesting systems and FeRAM (Ferroelectric Random Access Memory). But in a CMOS fab, PZT is unwanted because of the lead contamination risk, material compatibility issues, additional process complexity, and reliability concerns associated with ferroelectric materials. In modern CMOS fabs which aim to minimize contamination risks and simplify the manufacturing process, PZT is typically avoided in favor of more compatible and environmentally friendly alternatives for applications requiring piezoelectric or ferroelectric properties.

Fab-friendly ReRAM

The materials used for creating our ReRAM are already used as standard in CMOS flows. Such materials compatibility makes it easier for companies to adopt our ReRAM, as they already know how to deal with these materials, and normally already have the tools needed to work with them. This enables them to avoid high cost and potential issues with reliability or cross-contamination with other materials in their flow.

Since fabs are such delicate environments with extremely sensitive (and very expensive) tools, any change can be very costly and have significant impacts. Introducing “unfriendly” materials which are not commonly used in the fab (or not used at all), requires a deep understanding of them and how they impact the environment in the fab. It often requires new processing tools t and new manufacturing procedures. But most of all, these materials have the potential to contaminate the environment. All these reasons make such materials difficult to adopt and become a major hurdle for new technologies using them. This is a key reason for the failure of some of the competing ReRAM technologies.

The ‘Secret Sauce’ of Materials

The many components and pieces of IP within a semiconductor chip can be comprised of different materials.

For ReRAM, different types of metal oxides can be used as resistive materials, with choices made based on electrical performance and compatibility with existing CMOS technology. There are also inert metals added on the top and bottom electrode layers which are chosen for various technical reasons.

As a developer of ReRAM IP, there are many materials that we can select from that provide the performance needed within a standard CMOS flow. We’ve chosen those that are the fab-friendliest. And it’s not just about the specific materials themselves; we are able to combine materials under different conditions to achieve the best possible performance. This is enabled by the expertise of our Device and Process teams, including more than a dozen PhDs in Physics and Chemistry.

It’s also about the process itself. Manufacturing Weebit ReRAM adds two masks to the manufacturing flow, versus up to 10 added masks for flash. Choosing ReRAM translates to fewer layers, less waste, and a more environmentally friendly process. On top of this inherent advantage, the Weebit Process team focuses on how to manufacture the cell efficiently in different fabs and different process nodes.

As customers look to choose the right embedded NVM for their SoC, there are many factors that can affect their decision. When it comes to materials, choosing Weebit ReRAM is the friendliest option – from a cost, complexity and environmental perspective. When combined with our performance and reliability advantages, the decision is clear!

The post Living in a (Semiconductor) Material World appeared first on Weebit.

Low-power design is critical, especially for chips inside battery-operated IoT devices that must support applications for several years on one battery in a very small area. Embedded non-volatile memory (NVM) for these devices must have ultra-low-power, high endurance and high reliability to support continuous monitoring, logging and communicating of small amounts of data over the product’s lifetime.

Ultra-low-power embedded NVM like Weebit ReRAM (RRAM) can enable longer use times between recharges or battery replacements and help improve system energy efficiency. The low voltage levels used for memory transactions, coupled with ReRAM’s fast memory access time, greatly reduce power consumption. And with programming, standby, sleep, and very deep power-down ReRAM modes, as well as rapid wake-up from deep power-down, designers can enable near-zero leakage power of internal and external NVM. You can read more about this in my previous article, ‘How Low Can You Go? An Inside Look at Weebit ReRAM Power Consumption’.

By reducing power consumption, the memory subsystem can also allocate more power to other critical components to enhance overall system performance. Designers can take this advantage even further by implementing smart, power-aware system memory partitioning strategies. This includes dividing data intelligently across volatile and non-volatile memory resources to reduce the size of system SRAM.

Smart memory partitioning in practice

In a wearable sensor designed to monitor a specific health parameter, it is common to store code on external flash and then load code onto the local code SRAM from which the MCU then fetches the code. Each time the system wakes up to log and process data, there is MCU power consumption related to executing the Write cycles; as well as time and energy needed to load the code from the external flash into the code SRAM, and for the MCU to fetch the code. There is also power required to maintain the code SRAM or keep on the always-on logic for these operations.

Above: Typical MCU architecture with external flash

An alternative way to architect this would be using an eXecute in Place (XiP) architecture where on-chip ReRAM can be used to store code instead of the code SRAM, and the MCU can fetch the code directly from the ReRAM. This reduces system wake-up time and decreases power since there is no need to access the external flash. It is also possible to turn off the code ReRAM to further reduce power. Our calculations show that this can result in 30% power savings over the previously described traditional architecture.

In addition, instead of storing log data to external flash, we can store it into on-chip ReRAM, eliminating the external flash altogether. If we replace the on-chip code SRAM as well as part of the data SRAM with ReRAM, we can achieve a total of 60% power reduction, and a device that can last up to four years!

Finally, instead of logging the data into SRAM and storing processed data onto ReRAM, we can log processed data directly into ReRAM, thereby eliminating most of the on-chip SRAM. In this way we can reach a total of more than five years of lifetime for this application. With NVM like ReRAM, there is close to zero power consumption needed to retain the data during inactive states.

Above: Example medical device logging system with on-chip ReRAM for code and data

Enabling new use cases

Reconsidering the memory technology and architecture in a typical IoT sensor/medical logging device can enable advantages in terms of power consumption and device lifetime. This becomes even more important with a device that doesn’t have a battery. In a device using energy harvesting, a traditional architecture can be prohibitive. Using a combination of logging data in SRAM and uploading it to flash can actually consume more power than what’s available!

Advanced hearing aids, wireless earphones, pacemakers and other medical and wearable appliances that need over-the-air (OTA) firmware updates can also benefit. In our calculations, performing a chip erase and then programming the new code required for the OTA update requires more time and energy than what is available using a standard off-the-shelf ultra-low-power flash device.

Embedded NVM like ReRAM, coupled with smart memory partitioning, can improve the energy efficiency of battery operated and energy-harvesting ICs. In a new article in Electronics Weekly, I go into greater detail on the different architectures and power savings that can be achieved.

Read the full article here.

The post Enhancing IoT System Performance with Smart Memory Partitioning appeared first on Weebit.